1. How to deal with some theoretical conflicts in actual wiring?
Basically, it is right to divide and isolate the analog/digital ground. It should be noted that the signal trace should not cross the moat as much as possible, and the return current path of the power supply and signal should not be too large.
The crystal oscillator is an analog positive feedback oscillation circuit. To have a stable oscillation signal, it must meet the loop gain and phase specifications. The oscillation specifications of this analog signal are easily disturbed. Even if ground guard traces are added, the interference may not be completely isolated. Moreover, the noise on the ground plane will also affect the positive feedback oscillation circuit if it is too far away. Therefore, the distance between the crystal oscillator and the chip must be as close as possible.
Indeed, there are many conflicts between high-speed wiring and EMI requirements. But the basic principle is that the resistance and capacitance or ferrite bead added by EMI cannot cause some electrical characteristics of the signal to fail to meet the specifications. Therefore, it is best to use the skills of arranging traces and PCB stacking to solve or reduce EMI problems, such as high-speed signals going to the inner layer. Finally, resistance capacitors or ferrite bead are used to reduce the damage to the signal.

2. How to solve the contradiction between manual wiring and automatic wiring of high-speed signals?
Most of the automatic routers of strong wiring software have set constraints to control the winding method and the number of vias. The winding engine capabilities and constraint setting items of various EDA companies sometimes differ greatly.
For example, whether there are enough constraints to control the way of serpentine winding, whether it is possible to control the trace spacing of the differential pair, etc. This will affect whether the routing method of the automatic routing can meet the designer’s idea.
In addition, the difficulty of manually adjusting the wiring is also absolutely related to the ability of the winding engine. For example, the pushing ability of the trace, the pushing ability of the via, and even the pushing ability of the trace to the copper coating, etc. Therefore, choosing a router with strong winding engine capability is the solution.

3. About the test coupon.
The test coupon is used to measure whether the characteristic impedance of the produced PCB board meets the design requirements with TDR (Time Domain Reflectometer). Generally, the impedance to be controlled has two cases: single wire and differential pair.
Therefore, the line width and line spacing on the test coupon (when there is a differential pair) should be the same as the line to be controlled. The most important thing is the location of the grounding point during measurement.
In order to reduce the inductance value of the ground lead, the grounding place of the TDR probe is usually very close to the probe tip. Therefore, the distance and method between the signal measurement point and the ground point on the test coupon Must match the probe used.

4. In high-speed PCB design, the blank area of ​​the signal layer can be coated with copper, and how should the copper coating of multiple signal layers be distributed on the ground and power supply?
Generally, the copper plating in the blank area is mostly grounded. Just pay attention to the distance between the copper and the signal line when applying copper next to the high-speed signal line, because the applied copper will reduce the characteristic impedance of the trace a little. Also be careful not to affect the characteristic impedance of other layers, for example in the structure of dual strip line.

5. Is it possible to use the microstrip line model to calculate the characteristic impedance of the signal line on the power plane? Can the signal between the power supply and the ground plane be calculated using the stripline model?
Yes, the power plane and ground plane must be regarded as reference planes when calculating the characteristic impedance. For example, a four-layer board: top layer-power layer-ground layer-bottom layer. At this time, the characteristic impedance model of the top layer is a microstrip line model with the power plane as the reference plane.

6. Can test points be automatically generated by software on high-density printed boards under normal circumstances to meet the test requirements of mass production?
Generally, whether the software automatically generates test points to meet the test requirements depends on whether the specifications for adding test points meet the requirements of the test equipment. In addition, if the wiring is too dense and the rules for adding test points are strict, there may be no way to automatically add test points to each line. Of course, you need to manually fill in the places to be tested.

7. Will adding test points affect the quality of high-speed signals?
Whether it will affect the signal quality depends on the method of adding test points and how fast the signal is. Basically, additional test points (do not use the existing via or DIP pin as test points) may be added to the line or pulled a short line from the line.
The former is equivalent to adding a small capacitor on the line, while the latter is an extra branch. Both of these conditions will affect the high-speed signal more or less, and the extent of the effect is related to the frequency speed of the signal and the edge rate of the signal. The magnitude of the impact can be known through simulation. In principle, the smaller the test point, the better (of course, it must meet the requirements of the test tool) the shorter the branch, the better.